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Fully Enumerated Filter
Signal
In/Out
Port Width Bits
Description
coefficients with the new set of coefficients pointed by the input COEF_SEL.
In Reloadable Coefficient mode (COEF_TYPE = 1), the signal makes the
filter start using coefficients recently loaded in the auxiliary page.
COEF_SEL
In
4
Coefficient set selector. Identifies the pre-programmed fixed coefficient set to
be activated and used as the filter coefficients. This port is enabled only
when Multiple Coefficients mode is selected.
CLK
NGRST
In
In
1
1
Clock. Rising edge active. The core master clock.
Asynchronous reset. Active low. Resets all internal registers. The signal is
expected to follow the FPGA power-on.
RSTN
FIRO
DATAO_VALID
In
Out
Out
1
DATA_WIDTH +
COEF_WIDTH +
ceiling(log 2 TAPS)
1
Synchronous reset. Active low. Resets all internal registers.
Data output. The filtered data appear on this port. It is a full precision output.
For example, at 12-bit data, 15-bit coefficients, and 150 taps, the output
width = 12 + 15 + ceil(log2150) = 12 + 15 + 8 = 35 bits.
Output data valid. Active high. Indicates that a new output data sample is
present at the FIRO port
Figure 13 and Figure 14 on page 19 show examples of the core in Constant and Reloadable Coefficient
modes. Figure 15 shows Multiple Coefficients mode.
CoreFIR
input data
input data valid
DATAI
DATAI_VALID
FIRO
DATAO_VALID
output data
output data valid
COEFI
COEFI_VALID
COEF_ON
COEF_SEL
clock
synch reset
asynch reset
CLK
RSTN
NGRST
Figure 13 · Parallel Filter Constant Coefficient Configuration
18
CoreFIR v8.5 Handbook
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